1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and more particularly to an array substrate that reduces wavy noise and damages to an active layer, and a method of fabricating that array substrate.
2. Background of the Related Art
In the related art LCD devices, physical properties of liquid crystal molecules such as an optical anisotropic property and polarization properties are used to display images. The liquid crystal molecules have unique orientation characteristics resulting from their thin and long shape. An arrangement direction of the liquid crystal molecules is controlled by applying an electrical field to them. Accordingly, when the electric field is applied to the liquid crystal molecules, the polarization properties is changed according to the arrangement of the liquid crystal molecules to transmit light, thereby displaying the images on the LCD screen.
The LCD device includes a first substrate, a second substrate and a liquid crystal layer interposed therebetween. A common electrode and a pixel electrode are respectively formed on the first and second substrates. The first and second substrates may be referred to as a color substrate and an array substrate, respectively. The liquid crystal layer is driven by a vertical electric field induced between the common and pixel electrodes. The LCD device has excellent transmittance and aperture ratio.
Among the known types of LCD devices, active matrix LCD (AM-LCD) devices, which have thin film transistors (TFTs) arranged in a matrix form, are the subject of significant research and development because of their high resolution and superior ability in displaying moving images.
FIG. 1 is a schematic view of an LCD device according to the related art. As shown in FIG. 1, the LCD device 51 includes a first substrate 5, a second substrate 10 and a liquid crystal layer (not shown) interposed therebetween. The first and second substrates 5 and 10 are facing each other and spaced apart. A black matrix 6, a color filter layer including sub-color filters 7a, 7b and 7c, and a common electrode 9 are formed on the first substrate 5. The black matrix 6 has a lattice pattern and blocks light that transmits through the second substrate 10. Each of the sub-color filters 7a, 7b and 7c has one of red R, green G and blue B colors and the sub-color filters 7a, 7b and 7c are formed in the lattice patterns. The common electrode 9 of a transparent conductive material is formed on the black matrix 6 and the color filter layer 7.
A gate line 14 and a data line 26 are formed on the second substrate 10. The gate and data lines 14 and 26 intersect each other to define a pixel region P on the second substrate 10. A TFT T is formed in the pixel region P. The TFT T is connected to the gate and data lines 14 and 26. Although not shown, the TFT T includes a gate electrode, a semiconductor layer, a source electrode, and a drain electrode. The gate and source electrodes are connected to the gate line 14 and the data line 26, respectively. The source electrode is spaced apart from the drain electrode. Moreover, a pixel electrode 32 is formed in the pixel region P. And, the pixel electrode 32 is connected to the TFT T. The pixel electrode 32 is formed of a transparent conductive material, such as indium-tin-oxide (ITO) and indium-zinc-oxide (IZO). As mentioned above, an electric field is induced between the common electrode 9 and the pixel electrode 32 to drive the liquid crystal layer (not shown).
The related art method for fabricating an array substrate may includes five or six mask processes. For example, the related art five mask processes include the following steps. In a first mask process, the gate electrode and the gate line are formed on the second substrate. At the same time, a gate pad, which is formed at one end of the gate line, is formed on the second substrate. Then, a gate insulating layer is formed on an entire surface of the second substrate having the gate electrode and the gate line. In a second mask process, the semiconductor layer, which includes an active layer and an ohmic contact layer, is formed on the gate insulating layer. The semiconductor layer corresponds to the gate electrode. In a third mask process, the data line, the source electrode and the drain electrode are formed on the gate insulating layer and the semiconductor layer. The source and drain electrodes corresponds to the semiconductor layer. At the same time, a data pad, which is disposed at one end of the data line, is formed on the gate insulating layer. In a fourth mask process, a passivation layer having a drain contact hole is formed on the data line, the source electrode and the drain electrode. The drain contact hole exposes the drain electrode. In a fifth mask process, the pixel electrode is formed on the passivation layer. The pixel electrode is connected to the drain electrode through the drain contact hole.
Since the array substrate is fabricated through the complicated mask processes, risk of deteriorating some of the component increases and a production yield decreases. In addition, since fabrication time and cost increase, a competitiveness of product is reduced. To resolve these problems in the five mask process, a four mask process is suggested.
FIG. 2 is a plane view of one pixel region of the array substrate fabricated by a related art four mask process. As shown in FIG. 2, the gate line 62 and the data line 98 are formed on the subtrate 60. The gate and data lines 62 and 98 intersect each other to define the pixel region P on the substrate 60. The gate pad 66 is formed at one end of the gate line 62. A transparent gate pad terminal GPT is formed on the gate pad 66 and contacting the gate pad 66. The data pad 99 is formed at one end of the data line 98. A transparent data pad terminal DPT is formed on the data pad 99 and contacting the data pad 99.
A TFT T including a gate electrode 64, a first semiconductor layer 91, a source electrode 94 and a drain electrode 96 is disposed at a respective intersection of the gate and data lines 62 and 98. The gate electrode 64 is connected to the gate line 62 and the source electrode 94 id connected to the data line 98. The source and drain electrodes 94 and 96 are spaced apart from each other on the first semiconductor layer 91. A pixel electrode PXL is formed in the pixel region P and contacts the drain electrode 96.
A metal layer 97 having an island shape and contacting the pixel electrode PXL overlaps a portion of the gate line 62. The portion of the gate line 62 functions as a first storage electrode, the metal layer 97 functions as a second storage electrode, and a gate insulating layer (not shown) formed of a dielectric material disposed between the first and second storage electrodes functions as a storage capacitor Cst.
A second semiconductor layer 92 is formed under the data line 98, and a third semiconductor layer 93 is formed under the metal layer 97. Since the second semiconductor layer 92 extends from the first semiconductor layer 91 in the four mask process, the second semiconductor layer 92 has a same structure as the first semiconductor layer 91. A portion of an active layer of the first semiconductor layer 91 is not covered by the gate electrode 64 and is exposed to light generated from a backlight unit (not shown) under the substrate 60. And a portion of an active layer of the second semiconductor layer 92 is not covered by the data line 98 and is exposed to an ambient light. Namely, the active layer of the second semiconductor layer 92 protrudes beyond the data line 98. Since the active layer of the first semiconductor layer 91 is formed of amorphous silicon, a photo leakage current is generated due to the light from the backlight unit.
As a result, the TFT T is damaged due to the photo leakage current. Moreover, since the active layer of the second semiconductor layer 92 is also formed of amorphous silicon, a leakage current is also generated in the second semiconductor layer 92 due to the ambient light. The light leakage current causes a coupling of signals in the data line 98 and the pixel electrode PXL to generate wavy noise when displaying images. A black matrix (not shown) designed to cover the protruding portion of the second semiconductor layer 92 reduces aperture ratio of the LCD device.
FIGS. 3A and 3B are cross-sectional views taken along lines IIIa-IIIa and IIIb-IIIb of FIG. 2, respectively. As shown in FIGS. 3A and 3B, the first semiconductor layer 91 is formed under the source and drain electrodes 94 and 96. The second semiconductor layer 92 is formed under the data line 98. The second semiconductor layer 92 extends from the first semiconductor layer 91. The first semiconductor layer 91 includes an intrinsic amorphous silicon layer as an active layer 91a and an impurity-doped amorphous silicon layer as an ohmic contact layer 91b. The second semiconductor layer 92 includes an intrinsic amorphous silicon layer 92a and an impurity-doped amorphous silicon layer 92b. 
As shown in FIG. 3A, the first semiconductor layer 91 is connected to the second semiconductor layer 92, therefore, a portion of the active layer 91a can not be completely covered by the gate electrode 64. This portion of the active layer 91a is exposed to light generated from the backlight unit (not shown), thus a photo current is generated in the active layer 91a. And, this photo current becomes a leakage current in the TFT T and causes an abnormal leakage of voltage in the pixel region P, thereby damaging the TFT T. As shown in FIG. 3A, the active layer 91a is exposed through the ohmic contact layer 91b and is over-etched to reduce the impurities left on the active layer 91a, thus, the active layer 91a includes a sufficient thickness. Accordingly, the photo currents are generated in the TFT T and damage the TFT T.
Similarly, as shown in FIG. 3B, a portion of the intrinsic amorphous silicon layer 92a of the second semiconductor layer 92 under the data line 98 protrudes beyond the data line 98. When the protruding portion of the intrinsic amorphous silicon layer 92a is exposed to light generated from the backlight unit or the ambient light, it is repeatedly turned on and off, thus the light leakage current is generated. The light leakage current is coupled with the signal in the pixel electrode PXL. Accordingly, an arrangement of the liquid crystal molecules is abnormally distorted. Thus, undesired wave-shaped thin lines (a wavy noise) are displayed on screen.
Typically, a distance between the data line 98 and the pixel electrode PXL is approximately 4.75 μm in the related art LCD device fabricated by the five or six mask processes. The intrinsic amorphous silicon layer 92a of the second semiconductor layer 92 protrudes beyond the data line 98 by approximately 1.7 μm in the related art LCD device fabricated by the four mask process. Accordingly, a distance D between the data line 98 and the pixel electrode PXL is approximately 6.45 μm (=4.75 um+1.7 um) due to the protrusion of the intrinsic amorphous silicon layer 92a. Therefore, the pixel electrode PXL in the related art LCD device of four mask process is farther away from the data line 98 than in the five or six mask processes. In addition, a width W1 of a black matrix BM that shields the data line 98 and the distance D increases in the related art LCD device of four mask process. This increase in the width of the black matrix BM reduces the aperture ratio.
FIGS. 4A to 4G are cross-sectional views showing a related art fabricating process taken along line IIIa-IIIa of FIG. 2. FIGS. 5A to 5G are cross-sectional views showing a related art fabricating process taken along line V-V of FIG. 2. And, FIGS. 6A to 6G are cross-sectional views showing a related art fabricating process taken along line VI-VI of FIG. 2.
FIGS. 4A, 5A and 6A show a first mask process. As shown in FIGS. 4A, 5A and 6A, a gate line 62, a gate pad 66 and a gate electrode 64 are formed on a substrate 60 having a pixel region P, a switching region S, a gate pad region GP, a data pad region DP and a storage region C through a first mask process. The gate pad 66 is formed at one end of the gate line 62. The gate electrode 64 is connected to the gate line 62 and disposed in the switching region S. The gate pad 66 is disposed in the gate pad region GP. The gate line 62, the gate pad 66 and the gate electrode 64 are formed by depositing and patterning a first metal layer (not shown) using a first mask (not shown) as a pattering mask. The first metal layer includes material selected from conductive metallic material group having aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), and molybdenum (Mo). The first metal layer may have a double-layered structure.
FIGS. 4B to 4E, 5B to 5E and 6B to 6E show a second mask process. As shown in FIGS. 4B, 5B and 6B, a gate insulating layer 68, an intrinsic amorphous silicon layer 70, an impurity-doped amorphous silicon layer 72 and a second metal layer 74 are formed on the substrate 60 having the gate line 62. The gate insulating layer 68 is formed of an inorganic insulating material or an organic insulating material. The inorganic insulating material may include one of silicon nitride and silicon oxide, and the organic insulating material may include one of benzocyclobuene (BCB) and acrylate resin. The second metal layer 74 includes material selected from conductive metallic material group having aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), and molybdenum (Mo). The second metal layer 74 may have a double-layered structure.
A photoresist (PR) layer 76 is formed on the second metal layer 74. A second mask M is disposed over the photoresist layer 76. The second mask M has a transmitting portion B1, a blocking portion B2 and a half-transmitting portion B3. The transmitting portion B1 includes a relatively high light transmittance so that light through the transmitting portion B1 can change the chemical property of the PR layer completely. The blocking portion B2 shields light completely. The half-transmitting portion B3 includes a slit structure or a half-transmitting film. Accordingly, an intensity of light transmitting through the half-transmitting portion B3 can be lowered. As a result, light transmittance at the half-transmitting portion B3 is smaller than that of the transmitting portion B1 and is greater than that of the blocking portion B2.
A portion of second mask M where the half-transmitting portion B3 is sandwiched by two blocking B2 correspond to the switching region S on the substrate 60. The transmitting portion B1 corresponds to the gate pad region GP and the pixel region P, and the blocking portion B2 corresponds to the storage region C and the data pad region DP. The PR layer 76 is exposed to light transmitting through the second mask M.
Next, as shown in FIGS. 4C, 5C and 6C, first to third PR patterns 78a, 78b and 78c are formed in the switching region S, the data pad region DP and the storage region C, respectively. And, the second metal layer 74 is exposed by the first to third PR patterns 78a, 78b and 78c. The first PR pattern 78a has a step-like structure that a height of the first PR pattern 78a at a center portion is lowered due to the half-transmitting portion B3 of the second mask M. The second metal layer 74, the impurity-doped amorphous silicon layer 72 and the intrinsic amorphous silicon layer 70 are etched using the first to third PR patterns 78a to 78c as an etching mask. The second metal layer 74, the impurity-doped amorphous silicon layer 72 and the intrinsic amorphous silicon layer 70 are all etched simultaneously or etched individually depending on the metallic material of the second metal layer 74.
As shown in FIGS. 4D, 5D and 6D, first to third metal patterns 80, 82 and 86 are formed under the first to third PR patterns 78a, 78b and 78c, and first to third semiconductor patterns 90a, 90b and 90c are formed under the first to third metal patterns 80, 82 and 86. The second metal pattern 82 extends from the first metal pattern 80, and the third metal pattern 86 having an island shape is formed in the storage region C. The first to third semiconductor patterns 90a, 90b and 90c include an intrinsic amorphous silicon pattern 70a and an impurity-doped amorphous silicon pattern 72a. 
Next, the first to third PR patterns 78a, 78b and 78c are ashed such that the center portion of the first PR pattern 78a is removed to expose the first metal pattern 80. In addition, peripheral portions of the first to third PR patterns 78a, 78b and 78c are removed simultaneously. Accordingly, the first to third PR patterns become fourth to sixth PR patterns 79a, 79b and 79c exposing the first to third metal patterns 80, 82 and 86, respectively.
As shown in FIGS. 4E, 5E and 6E, the first to third metal patterns 80, 82 and 86 and the impurity-doped amorphous silicon layer 72a are etched using the fourth to sixth PR patterns 79a to 79c. The first metal pattern 80 (of FIG. 4D) in the switching region S is etched to form source and drain electrodes 94 and 96, the second metal pattern 82 (of FIG. 6D) in the data pad region DP is etched to form a data line 98 and a data pad 99, and the third metal pattern 86 (of FIG. 4D) in the storage region C is etched to form a metal layer 97. The intrinsic amorphous silicon layer 70a (of FIG. 4D) and the impurity-doped amorphous silicon layer 72a (of FIG. 4D) of the first semiconductor pattern 90a (of FIG. 4D) are etched to form an active layer 91a and an ohmic contact layer 91b, respectively. The active layer 91a and the ohmic contact layer 91b forms a first semiconductor layer 91. The active layer 91a is exposed through the ohmic contact layer 91b. The active layer 91a is also over-etched such that the impurities are removed from the active layer 91a. 
In addition, the second and third semiconductor patterns 90b and 90c (of FIGS. 6D and 4D) are etched to form second and third semiconductor layers 92 and 93, respectively. An overlapped portion of the gate line 62 (first storage electrode) and the metal layer 97 (second storage electrode) forms the storage capacitor Cst with the gate insulating layer 68. Thereafter, the fourth to sixth PR patterns 79a, 79b and 79c are removed.
FIGS. 4F, 5F, and 6F show a third mask process. A passivation layer PAS is formed on the substrate 60 having the data line 98. The passivation layer PAS is patterned using a third mask (not shown) to form a drain contact hole CH1 exposing the drain electrode 96, a storage contact hole CH2 exposing the metal layer 97, and a data pad contact hole CH4 exposing the data pad 99. Furthermore, the passivation layer PAS and the gate insulating layer 68 are patterned using the third mask (not shown) to form a gate pad contact hole CH3 exposing the gate pad 66.
FIGS. 4G, 5G and 6G show a fourth mask process. A transparent conductive material is deposited on the passivation layer PAS and patterned through a fourth mask (not shown) to form a pixel electrode PXL, a gate pad terminal GPT and a data pad terminal DPT. The pixel electrode PXL contacts the drain electrode 96 within the drain contact hole CH1 and the metal layer 97 within the storage contact hole CH2. The gate pad terminal GPT contacts the gate pad 66 within the gate pad contact hole CH3, and the data pad terminal DPT contacts the data pad 99 within the data pad contact hole CH4.
Through the above four mask process, the related art array substrate is fabricated. Production costs and production time are saved by the related art four mask process. However, since the intrinsic amorphous silicon layer of the second semiconductor layer protrudes beyond the data line, noise is generated and the aperture ratio is reduced. In addition, since the active layer is connected to the intrinsic amorphous silicon layer of the second semiconductor layer, a portion of the active layer is not covered by the gate electrode. Accordingly, the light leakage current is generated in the thin film transistor. Furthermore, because a thick active layer should be formed in consideration of the over-etching, fabrication time and product cost increase. Moreover, the related art array substrate fabricated by the fourth mask process requires a black matrix having a width greater than that of the five mask process, aperture ratio is further reduce.